Institut für Rechnerarchitektur
und Parallelrechner
Dr. Sven Beyer
Universität des Saarlandes   Gebäude E1 3
FR 6.2 Informatik    
Postfach 151150    
D-66041 Saarbrücken   Fax: +49 (0)681 302-4290
Germany   eMail: sbeyer@cs.uni-saarland.de
 
 
Lebenslauf
1975 Geboren in Saarlouis
1995 Abitur am Peter-Wust-Gymnasium in Merzig
1996 - 2000 Studium der Informatik an der Universität des Saarlandes
1998 Vordiplom in Mathematik
2000 Diplom in Informatik
2000 - 2005 Promotion an der Universität des Saarlandes
 
Forschungsinteressen
Formale Verifikation
Hardware Design
 
Private Homepage
http://www.tzwaenn.de
 
Publikationen
Beyer, S. and Jacobi, C. and Kröning, D. and Leinenbach, D. and Paul, W.J.   EE BibTeX
Putting it all together - Formal Verification of the VAMP.
In STTT Journal, Special Issue on Recent Advances in Hardware Verification,
Springer, 2006.
 
Beyer, Sven   BibTeX
Putting it all together - Formal Verification of the VAMP.
Dissertation, Saarland University, Saarbrücken, 2005.
 
Ayewah, N. and Beyer, S. and Kikkeri, N. and Seidel, P.-M.   EE BibTeX
Challenges in the Formal Verification of Complete State-of-the-Art Processors.
In International Conference on Computer Design,
San Jose
2005.
 
Beyer, S. and Böhm, P. and Gerke, M. and Hillebrand, M. and In der Rieden, T. and Knapp, S. and Leinenbach, D. and Paul, W.J.   EE BibTeX
Towards the Formal Verification of Lower System Layers in Automotive Systems.
In 23nd IEEE International Conference on Computer Design: VLSI in Computers and Processors (ICCD 2005), 2-5 October 2005, San Jose, CA, USA, Proceedings,
pages 317-324, IEEE, 2005.
ISBN 0-7695-2451-6
 
Beyer, S. and Jacobi, C. and Kröning, D. and Leinenbach, D. and Paul, W.J.   EE BibTeX
Instantiating uninterpreted functional units and memory system: functional verification of the VAMP.
In Geist, D. and Tronci, E., editors, CHARME 2003,
volume 2860 of LNCS, pages 51-65, Springer, 2003.
 
Berg, C. and Beyer, S. and Jacobi, C. and Kröning, D. and Leinenbach, D.   BibTeX
Formal Verification of the VAMP Microprocessor (Project Status).
In Charatonik, Witold and Ganzinger, Harald, editors, Symposium on the Effectiveness of Logic in Computer Science (ELICS02),
pages 31-36, Max-Planck-Institut für Informatik, 2002.
 
Beyer, S. and Jacobi, C. and Kroening, D. and Leinenbach, D.   BibTeX
Correct Hardware by Synthesis from PVS.
2002.
unpublished, available at http://busserver.cs.uni-sb.de/publikationen/BJKL02.pdf
 
Beyer, Sven   BibTeX
Entwurf einer PCI-Karte als Schnittstelle zwischen SB-PRAM und PC.
Diplomarbeit, Universität des Saarlandes, 2000.